The present disclosure relates generally to image data processing and, more particularly, to implementation of circuitry in an image data processing pipeline.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
To present visual representations of information, an electronic device may utilize an electronic display to display one or more images (e.g., pictures or image frames) based on corresponding image data. In particular, the electronic display may adjust luminance of its display pixels based on target luminance indicated by the image data. In some instances, image data may be processed before being using to display a corresponding image, for example, to facilitate improving perceived image quality when the corresponding image is displayed on an electronic display.
To facilitate improving processing latency, image data may be processed using pipelined circuitry, for example, implemented as one or more processing blocks in an image data processing pipeline. However, in some instances, processing image data using pipelined circuitry may limit operational flexibility, for example, when an image data processing pipeline is implemented with a single data path through its processing blocks. Moreover, in some instances, processing image data using pipelined circuitry may limit power consumption efficiency, for example, when electrical power is supplied to each processing block in an image data processing pipeline regardless of targeted functions to be performed by the image data processing pipeline.